𝗜𝗣 cores

Vortex - a full-system RISCV-based GPGPU processor

Specs
▫️Support RISC-V RV32IMF ISA
▫️Fully scalable: 1 to 32 cores with optional L2 and L3 caches
▫️OpenCL 1.2 Support
▫️FPGA target: Intel Arria 10 @200 MHz

💾 https://github.com/vortexgpgpu/vortex

#verilog #GPGPU #GPU #FPGA #LLVM
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Thank you to everyone of you! 🙏🏻

S-Link - a lightweight chiplet/chip-to-chip controller. S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication.

S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.

Features:
▫️Mult-lane support (upto 128+)
▫️128b/130b encoding
▫️Parameterizable Application Data Widths
▫️Configurable Attributes for fine tuning link controls and/or active link management
▫️ECC/CRC for error checking of packet headers and payload data
▫️Parameterizable pipeline stages to optimize for frequency and/or power

💾 https://github.com/waviousllc/wav-slink-hw

#chiplet #protocol #verilog
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XiangShan - mature (almost 6000 commits) high-performance RISC-V processor by Institute of Computing Technology, Chinese Academy of Sciences.

💾 https://github.com/OpenXiangShan/XiangShan
📄 https://github.com/OpenXiangShan/XiangShan-doc

#ISA #RISCV #scala #chisel #CPU #FPU
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Process-Voltage-Temperature (PVT) Sensors with MCU - a collection of open-source circuits and software tools for PVT monitoring in custom ICs.

💾 https://github.com/scale-lab/PVTsensors

#verilog #asic #PVT #cmos #RISCV #precess
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LoRa Modulator - a custom LoRa modulator that supports different bandwidths and spreading factors (SF) on Lattice ECP5 FPGA and I/Q interface with AT86RF215 RF radio.

💾 https://github.com/uw-x/lora-modulator

#verilog #RF #LoRa #modulator #transmitter
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Vortex - a full-system RISCV-based GPGPU processor.

Specs
▫️Support RISC-V RV32I ISA
▫️Fully scalable: 1 to 16 cores with optional L2 and L3 caches
▫️OpenCL 1.2 Support
▫️FPGA target: Intel Arria 10 @200 MHz

💾 https://github.com/himanshu5-prog/vortexGPU

#verilog #GPGPU #GPU #FPGA #LLVM
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SimpleVOut - FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

Links:
▫️ Sources

#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
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FPU Generator - a Floating Point Adder/Multiplier/Multiply-Accumulate generator and testbench.

Links:
▫️ Sources

#perl #matlab #FPU #FloatingPoint
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Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.

▫️lfsr.v - Parametrizable combinatorial LFSR/CRC module
▫️lfsr_crc.v - Parametrizable CRC computation wrapper
▫️lfsr_descramble.v - Parametrizable LFSR self-synchronizing descrambler
▫️lfsr_prbs_check.v - Parametrizable PRBS checker wrapper
▫️lfsr_prbs_gen.v - Parametrizable PRBS generator wrapper
▫️lfsr_scramble.v - Parametrizable LFSR self-synchronizing scrambler

Links:
▫️ Sources

#verilog #python #MyHDL #LFSR #CRC
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GLIP - The Generic Logic Interfacing Project.

GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP.

Features
▫️Easy FIFO-based communication, abstracting away all low-level details
▫️Support for different communication channels through backends
▫️Side-channel communication (e.g. reset signals)
▫️Developed on and for Linux

Links:
▫️ Documentation
▫️ Sources

#verilog #SV #JTAG #FIFO #USB
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parser-gen - Network packet parser generator. This generator produces synthesizable SystemVerilog.

It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.

Links:
▫️ Documentation
▫️ Sources

#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
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[WiP] PCI2Nano - An open source FPGA PCI (not PCI-E) core, a 8250-Compatible PCI-based UART core and Nios II example design driving the UART.

Actually this is a turnkey set of open source design files and reference information for anyone to be able to start tinkering with PCI/PCIe on low end FPGAs. If you have a desire to interface to a host which supports PCIe and would like a quick way to design PCI functions which interface to the host, this project may be for you!

Links:
▫️ gateware
▫️ hardware

#PCI #verilog #UART #8250 #NIOS

[WiP] ARM_Implementation - an implementation of ARM processor in Verilog.

Features:
▫️ Pipeline
▫️ Hazard Detection
▫️ Forwarding Unit

https://github.com/gsoosk/ARM_Implementation

#ARM #CPU #verilog

bladeRF-wiphy - project is an open-source IEEE 802.11 compatible software defined radio VHDL modem. The modem is able to modulate and demodulate 802.11 packets (the protocol WiFi is based on), and can be adapted to various FPGA SDR platforms.

Features:
◦ IEEE 802.11 compatible FPGA based PHY receiver and transmitter
◦ Linux mac80211 MAC integration
◦ RX and TX monitor mode support
◦ Hardware Distributed Coordination Function (DCF) allows quick turn-around time ACKs
◦ High-performance equalizer – implements Zero Forcing (ZF) and optionally Decision Feedback Equalizer (DFE)

Links:
◦ technical write-up
◦ sources

#VHDL #OFDM #PHY #802.11 #BladeRF #WiFi

VerCoLib-PCIe - The Versatile Communication Library is a collection of VHDL modules to enable DMA data transfer over PCIe.

◦ Doc
◦ Src

#PCIe #DMA #Xilinx #VHDL #Vivado #VUnit
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Full AXI VHDL verification model -
UVVM (the Open Source Universal VHDL Verification Methodology) has just released a free and open source VHDL verification model for AXI4. It can be accessible from UVVM repository and be used in any VHDL testbench - even inside an old legacy testbench if you like - or together with other VHDL verification systems.

The AXI4 model has full support for independent channels, burst transfers and out of order transmissons. The UVVM AXI4-lite has also been upgraded to allow independent channels. This means UVVM now provides free and open source VHDL verification models for AXI4, AXI4-lite and AXI4-stream.


#VHDL #UVVM #AXI #AMBA #BFM #verification
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A good entry point to CDC topic - from list of interesting documents explaining in depth CDC topics to gathering basic Clock domain crossing RTL modules, like:
▫️ IO debouncer
▫️ Simple synchronization thru 2 FFDs
▫️ Pulse synchronizer (with and w/o handshake)
▫️ Data bus synchronizer with recirculation mux
▫️ Asynchronous dual-clock FIFO (as submodule)

https://github.com/dpretet/cdc

#CDC #pulse #synchronizer #FF #fifo #SV #verilog
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SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.

Links:
▫️ sources
▫️ documentation

#VHDL #library #STL #primitives
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Verilog Audio Controller is a basic audio controller providing I2S, SPDIF, and DAC outputs.
Simple to drive AXI4-L register interface, with built in 2048 entry buffer and interrupt on programmable threshold.

Features
▫️SPDIF tx supporting 16-bit data @ 44.1KHz or 48KHz
▫️I2S master (SCK, SDATA, WS)
▫️2 channel sigma-delta DAC outputs
▫️AXI4-L register interface
▫️8KB RAM buffer inferred (maps to BRAM)
▫️Programmable interrupt threshold
▫️Single interrupt output

https://github.com/ultraembedded/core_audio

#I2S #SPDIF #DAC #audio #verilog
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