Full AXI VHDL verification model -
UVVM (the Open Source Universal VHDL Verification Methodology) has just released a free and open source VHDL verification model for AXI4. It can be accessible from UVVM repository and be used in any VHDL testbench - even inside an old legacy testbench if you like - or together with other VHDL verification systems.

The AXI4 model has full support for independent channels, burst transfers and out of order transmissons. The UVVM AXI4-lite has also been upgraded to allow independent channels. This means UVVM now provides free and open source VHDL verification models for AXI4, AXI4-lite and AXI4-stream.


#VHDL #UVVM #AXI #AMBA #BFM #verification
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