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𝗜𝗣 cores 𝗜𝗣 cores @ipcores · 1.2K subscribers
Post #110 3.14K
fpga_linear_time_sorter - a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially

This algorithm is fast, since the sorting itself is done in parallel while the data is being input serially. It is sorted and ready to be read back immediately following the last write transfer.

A 256-length, 8-bit sorter costs approximately 5500 logical elements on an Altera Cyclone IV.

Links:
💾 https://github.com/Poofjunior/fpga_fast_serial_sort

#algo #sort #sorting
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