Floating Point Clock Divider is a 24.16 (m.n) bit floating point clock divider (actually it is a fixed point fractional divider).

Features
▫️Resulting frequency precision down to the 0.01Hz
▫️calculating PPM error
▫️calculating jitter spec

Links
💾 https://github.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider
📄 https://www.eevblog.com/forum/fpga/verilog-floating-point-clock-divider-release/

#verilog #DIV #FP #clock #divider
@ipcores