𝗜𝗣 cores: “XiangShan - mature (almost 6000 commits) high-performance RISC-V proce…” · TGViewer

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Post #88 3.61K Jun 30, 2021, 16:20 UTC

XiangShan - mature (almost 6000 commits) high-performance RISC-V processor by Institute of Computing Technology, Chinese Academy of Sciences.

💾 https://github.com/OpenXiangShan/XiangShan
📄 https://github.com/OpenXiangShan/XiangShan-doc

#ISA #RISCV #scala #chisel #CPU #FPU
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