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𝗜𝗣 cores 𝗜𝗣 cores @ipcores · 1.2K subscribers
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Verilog Audio Controller is a basic audio controller providing I2S, SPDIF, and DAC outputs.
Simple to drive AXI4-L register interface, with built in 2048 entry buffer and interrupt on programmable threshold.

Features
▫️SPDIF tx supporting 16-bit data @ 44.1KHz or 48KHz
▫️I2S master (SCK, SDATA, WS)
▫️2 channel sigma-delta DAC outputs
▫️AXI4-L register interface
▫️8KB RAM buffer inferred (maps to BRAM)
▫️Programmable interrupt threshold
▫️Single interrupt output

https://github.com/ultraembedded/core_audio

#I2S #SPDIF #DAC #audio #verilog
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