TGViewer
𝗜𝗣 cores 𝗜𝗣 cores @ipcores · 1.2K subscribers
Post #82 2.65K
Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.

▫️lfsr.v - Parametrizable combinatorial LFSR/CRC module
▫️lfsr_crc.v - Parametrizable CRC computation wrapper
▫️lfsr_descramble.v - Parametrizable LFSR self-synchronizing descrambler
▫️lfsr_prbs_check.v - Parametrizable PRBS checker wrapper
▫️lfsr_prbs_gen.v - Parametrizable PRBS generator wrapper
▫️lfsr_scramble.v - Parametrizable LFSR self-synchronizing scrambler

Links:
▫️ Sources

#verilog #python #MyHDL #LFSR #CRC
@ipcores
  • 👍 1
More from @ipcores
  1. Mar 24, 2025Floating Point Clock Divider is a 24.16 (m.n) bit floating point clock divider (actually i…
  2. Sep 13, 2024fpga_linear_time_sorter - a parallel sorting algorithm implemented in hardware that sorts…
  3. Sep 10, 2024Channel name was changed to «𝗜𝗣 cores»
  4. Sep 10, 2024FpOC - FPGA based Field Oriented Control (FOC) for driving Permanent Magnet Synchronous Mo…
  5. Apr 24, 2024Wupper - PCIe Gen3/Gen4/Gen5 DMA controller for Xilinx FPGA Features ▫️Specifically design…
  6. Apr 9, 2024Library that supports IEEE754-2008 floating point arithmetic with a parametrizable mantiss…
Threads Profile ViewerView any public Threads profile without an account.Open ThreadLook →Writing with AI? Make it sound human.Metric37 rewrites AI drafts so they read naturally. Free AI detector, 1,500 words free.Try Metric37 →