parser-gen - Network packet parser generator. This generator produces synthesizable SystemVerilog.

It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.

Links:
▫️ Documentation
▫️ Sources

#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
@ipcores