TGViewer
𝗜𝗣 cores 𝗜𝗣 cores @ipcores · 1.2K subscribers
Post #95 3.43K
open5G_rx - a synthesizable verilog HDL core for a 5G NR lower phy receiver.

Implemented:
▫️ Decimator
▫️ PSS correlator
▫️ Peak detector
▫️ PSS detector
▫️ FFT demodulator
▫️ SSS detector
▫️ Frame sync
▫️ Channel estimator
▫️ Ressource grid subscriber
▫️ AXI-DMAC


💾 https://github.com/catkira/open5G_rx

#SV #5G #DSP #FFT #ORAN
@ipcores
  • 👍 11
  • ❤ 4
  • 🔥 4
  • 😱 4
  • ⚡ 1
More from @ipcores
  1. Mar 24, 2025Floating Point Clock Divider is a 24.16 (m.n) bit floating point clock divider (actually i…
  2. Sep 13, 2024fpga_linear_time_sorter - a parallel sorting algorithm implemented in hardware that sorts…
  3. Sep 10, 2024Channel name was changed to «𝗜𝗣 cores»
  4. Sep 10, 2024FpOC - FPGA based Field Oriented Control (FOC) for driving Permanent Magnet Synchronous Mo…
  5. Apr 24, 2024Wupper - PCIe Gen3/Gen4/Gen5 DMA controller for Xilinx FPGA Features ▫️Specifically design…
  6. Apr 9, 2024Library that supports IEEE754-2008 floating point arithmetic with a parametrizable mantiss…
Threads Profile ViewerView any public Threads profile without an account.Open ThreadLook →Writing with AI? Make it sound human.Metric37 rewrites AI drafts so they read naturally. Free AI detector, 1,500 words free.Try Metric37 →