SVLogger - A SystemVerilog logger to help designers to log events in a circuit during a simulation in a consistent way. SVLogger is a simple class, easy to instantiate and use, with no dependencies.

💾 https://github.com/dpretet/svlogger
📄 https://github.com/dpretet/svlogger/tree/main/example

#logger #logging #simulation #verification #debug #sv #systemverilog #icarus
@ipcores