A high performance streaming FFT core based on Bailey's 4-step large FFT algorithm (focused on speed optimizing: Fmax is up to 30% higher than Xilinx FFT IP)

Data input/output are continuous with no gaps between frames. Currently only supporting power-of-two sizes and fixed point data.

Top level VHDL code is generated by the script codegen/gen_fft.py.

https://github.com/owocomm-0/fpga-fft

#FFT #DSP #VHDL #generator #python #multicycle_path