Piplined FFT Core - configurable C++ generator of Verilog FFT cores.

The FFT generated by this project is very configurable. By simple adjustment of a command line parameter, the FFT created will either be a forward FFT or an inverse FFT. The number of bits processed, kept, and maintained by this FFT are also configurable. Even the number of bits used for the twiddle factors, or whether or not to bit reverse the outputs, are all configurable parts to this FFT core.

https://github.com/ZipCPU/dblclockfft

#DSP #FFT #generator #verilog