Lightweigth USB Core - core that would be similar to the SIE you find in classic microcontrollers that support USBs. That means it requires a soft core to implement the actual USB stack, the hardware itself only handle up to the transaction layer of USB.

It's designed to be small but still allow full flexibility of what kind of device it implements, supports all types of transfers, all packet sizes and any combination of end points without having to change the hardware configuration at all.

Features:
◦ 10 BRAM, 390 FF and 530 LUT4
◦ Clocked at 48 MHz
◦ Wishbone interface for the CSRs and Buffer Descriptors

Links:
◦ Doc
◦ Src

#USB #iCE40 #FPGA #verilog #PHY