HDMI Out - SystemVerilog code for HDMI 1.4a video/audio output on an FPGA. To support audio and other HDMI-only functionality, a true HDMI signal must be sent. The code in this repository lets you do that without having to license an HDMI IP block from anyone.

◦ 24-bit color
◦ Data island packets
◦ Null packet
◦ ECC with BCH systematic encoding GF(2^8)
◦ Audio clock regeneration
◦ L-PCM audio 2-channel
◦ Audio InfoFrame
◦ Video formats 1, 2, 3, 4, 16, 17, 18, 19
◦ VGA text mode
◦ IBM 8x16 font
◦ Double Data Rate I/O (DDRIO)
◦ Supports up to 1920x1080@60Hz

https://github.com/hdl-util/hdmi

#HDMI #Altera #SystemVerilog