TGViewer
𝗜𝗣 cores 𝗜𝗣 cores @ipcores · 1.2K subscribers
Post #47 1.99K
Nyuzi - an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like deep learning and image processing.

This GPGPU includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

High level features:
◦ Multiple cores with cache coherence
◦ Hardware multithreading
◦ Wide vector floating point SIMD with predicated execution
◦ Virtual memory

src: https://github.com/jbush001/NyuziProcessor
doc: https://github.com/jbush001/NyuziProcessor/wiki

#SV #GPGPU #FPGA #LLVM
More from @ipcores
  1. Mar 24, 2025Floating Point Clock Divider is a 24.16 (m.n) bit floating point clock divider (actually i…
  2. Sep 13, 2024fpga_linear_time_sorter - a parallel sorting algorithm implemented in hardware that sorts…
  3. Sep 10, 2024Channel name was changed to «𝗜𝗣 cores»
  4. Sep 10, 2024FpOC - FPGA based Field Oriented Control (FOC) for driving Permanent Magnet Synchronous Mo…
  5. Apr 24, 2024Wupper - PCIe Gen3/Gen4/Gen5 DMA controller for Xilinx FPGA Features ▫️Specifically design…
  6. Apr 9, 2024Library that supports IEEE754-2008 floating point arithmetic with a parametrizable mantiss…
Threads Profile ViewerView any public Threads profile without an account.Open ThreadLook →Writing with AI? Make it sound human.Metric37 rewrites AI drafts so they read naturally. Free AI detector, 1,500 words free.Try Metric37 →