OpenOFDM - implementation of 802.11 OFDM decoder.
In a nutshell, the top level dot11 Verilog module takes 32-bit I/Q samples (16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling rate is 20 MSPS and the clock rate is 100 MHz.
Features:
◦ Full support for legacy 802.11a/g
◦ Support 802.11n for MCS 0..7@20MHz bandwidth
◦ Cross validation with included Python decoder
https://github.com/jhshi/openofdm
#verilog #OFDM #PHY #802.11 #USRP #WiFi
Post #46
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