USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

Current solutions for USB3 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A) or external FIFO (FTDI FT60X or Cypress FX3). With this project, we want to see if it's possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip).

https://github.com/enjoy-digital/usb3_pipe

#USB3 #PIPE #PHY #verilog #LiteX #python #Xilinx #Lattice