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𝗜𝗣 cores 𝗜𝗣 cores @ipcores · 1.2K subscribers
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The AMBA Bus Protocol Assertions is a verification and validation product designed to work with a range of different user environments and usage scenarios. The underlying goal is to provide protocol specific SystemVerilog assertions for the AMBA v3 & v4: ACE, AXI3, AXI4, AXI4-Lite and AXI4-Stream protocols.

Features:
◦ Support for the latest version of the AXI Specification
◦ Support for separate parameterisation for read and write ID widths
◦ Enhancements to end of simulation checks

This release has been developed and tested:
◦ SystemVerilog v3.1a
◦ Mentor ModelSim SE 10.1a
◦ Cadence Incisive 11.10.008
◦ Synopsys VCS 2011.12-3

Download links:
◦ AMBA 3 AXI3 Protocol Assertions
◦ AMBA 4 AXI4 Protocol Assertions
◦ AMBA 4 ACE Protocol Checker
◦ [All downloads required registration]

#AMBA #AXI #AXIlite #AXIS #SVA #SV #BFM #verification #ProtocolChecker
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