Verilog implementation of DisplayPort protocol for FPGA

Resolution| Lanes |Eff.Pix.clock
----------+-------+-------------
800x600   |   1   |  40.00 MHz
800x600   |   2   |  40.00 MHz
800x600   |   3   |  40.00 MHz
1280x720  |   1   |  74.25 MHz
1920x1080 |   2   | 148.50 MHz
3240x2160 |   2   | 165.00 MHz

https://github.com/hamsternz/DisplayPort_Verilog

#DisplayPort #verilog #video #FullHD