PonyLink - a bi-directional chip-to-chip interface that is using only a single signal wire between the two chips. Naturally this wire is used in a half-duplex fashion. For faster link speeds the use of a #LVDS pair is recommended. The cores are tested on #Xilinx Series 7 and #Lattice iCE40 FPGAs.

On the chip-facing side #PonyLink provides a transmit and receive #AXI Stream as well as 8 GPIO inputs and 8 GPIO outputs. PonyLink handles all the low-level tasks, including flow control and detection of failed transfers and automatic resend.

The main features of the core are that it only requires one single data line between the chips and that it can operate on resonable data rates (compared to the clock rates of the clocks driving the cores, usually over 0.5 MBit/s per MHz).

Features:
- typical net data rates of over 100 MBit/s at 166 MHz
- can utilize up to 4x serdes hardware for higher link speed
- support for any #AXIS TDATA and TUSER width and TLAST signal
- bi-directional communication over a single data line (usually LVDS)
- works without a dedicated hardware block for clock recovery
- dc-free signaling, allowing for caps or magnetics in the link
- embedded clock and control signals (using #8b10b encoding)

https://github.com/cliffordwolf/PonyLink
https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt
#verilog #python #protocol #serialinterface
@ipcores