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USB3 core:
USB2/ULPI & USB3/PIPE are working.

The design currently uses a TUSB1310A for interfacing with the USB3.0 connector. Future plans include replacing this part using the high speed transceivers (GTPs/GTXs) found in Artix-7/Kintex-7 FPGAs.

https://github.com/enjoy-digital/daisho

#USB2 #USB3 #verilog #TUSB1310A #Xilinx
GitHub GitHub - enjoy-digital/daisho: Test of the USB3 IP Core from Daisho on a Xilinx device Test of the USB3 IP Core from Daisho on a Xilinx device - enjoy-digital/daisho
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