DDR3 memory controller that does not depend on any non-documented features of Xilinx FPGA and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted modules. Everything in plain Verilog and constraints.

https://github.com/Elphel/eddr3
https://blog.elphel.com/2014/06/ddr3-memory-interface-on-xilinx-zynq-soc-free-software-compatible/
#DDR3 #Xilinx #AXI