An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components

In this work, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured.

Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC.

The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3.

Links:
💾 https://github.com/LukiLeu/FPGA_ADC
📄 https://dl.acm.org/doi/10.1145/3431920.3439287

#ADC #VHDL #TDC
@ipcores