Newest x86 APX extension - will it trigger new calling conventions standard?

For those that don't follow - this is the first new x86 extensions that ***doesn't*** have anything to do with vector or tensor instructions - it is about the core CPU and its ISA.

It ***doubles*** the general register set to 32 (from previous 16), introduces 3-operand instructions, new 64-bit offset jumps, new jump prediction improvements etc etc.

But all this seems to be hampered by existing call conventions for x86_64, which presumes 16GPR set.

It seems that much could be gained it the compiler could use extra GPRs for parameters when calling the given function.

OTOH, this would be incompatible with machines without APX.

So, what is to be done ? Maybe use function multiversioning mechanism to keep two sets of function entries or something ?

Or will whole thing be ignored and calling convention will stay the same ?

EDIT:\
I'm not talking about the compiler ability to emit new instructions and use new registers in the code.\
Ofcourse new compiler will have support for them from the start, that's how it's usually done.\
It's about having the standard in place to allow the compiler to make advantage of new facilities hen ***calling*** functions, so that it can have more parameters in registers, more options for inlining functions etc - all done in standard, interoperable way, so that one can use precompiled libraries etc.

https://redd.it/1wrq2s7
@r_linux