OpenVAF - an innovative Verilog-A compiler for use in circuit simulator. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.

Features:
▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%

OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models

Links:
📄 openvaf.semimod.de/
💾 github.com/pascalkuthe/OpenVAF

#simulation #model #veriloga
@fpgasic