Logic - CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Features:
▫️Cross platform, cross IDE
▫️No need to create separate scripts for simulation and synthesis
▫️No need to create separate scripts for different tools (Quartus, Vivado, ModelSim, ...)
▫️Supports incremental compilation
▫️Supports parallel compilation
▫️Maintain the same file consistency between simulation and synthesis for different tools
▫️Share the same HDL source code base and IP cores for various FPGA projects
▫️Integration with CI and CD like Jenkins, Hudson, GitLab, etc.
▫️Run RTL unit tests under ctest: pass/fail, time execution, timeout, parallel execution, tests selection
▫️Run the same unit tests with different parameters
▫️Easy to integrate with other projects as git submodule
▫️Custom UVM printers: JSON
▫️Modern HDL testing library written in C++11 using UVM-SystemC
▫️Support for Clang 3.5+
▫️Support for GCC 4.9+

💾 https://github.com/tymonx/logic
📄 https://github.com/tymonx/logic/wiki

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