Silice - A language for hardcoding Algorithms into FPGA hardware

It provides a thin abstraction above Verilog (a typical hardware description language), simplifying design without loosing precise control over the hardware. It gives the (optional) ability to write parts of your design as sequences of operations, subroutines that can be called, and to use control flow statements such as while and break. At the same time, Silice lets you fully exploit the parallelism of FPGA architectures, describing operations and algorithms that run in parallel and are precisely in sync.

💾 https://github.com/sylefeb/Silice

#FPGA #HLS #language
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