CACTI is an integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. By integrating all these models together, users can have confidence that tradeoffs between time, power, and area are all based on the same assumptions and, hence, are mutually consistent. CACTI is intended for use by computer architects to better understand the performance tradeoffs inherent in memory system organizations.

Power, delay, area, and cycle time model for
▫️ direct mapped caches
▫️ set-associative caches
▫️ fully associative caches
▫️ Embedded DRAM memories
▫️ Commodity DRAM memories

💾 https://github.com/HewlettPackard/cacti
📄 https://hpl.hp.com/research/cacti/


#memory #cache #PPA #estimation
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