Verification Haven

Welcome to the latest entry in my blog: Unhinged assignment. This post takes you on a journey that begins with the fundamentals of non-blocking assignments and gradually immerses you in the horrific fascinating world of indeterminism and delta-cycle shenanigans.

How many lines does one need to break VCS? Not much.

module tb;
  logic a = 0;
  logic b = 0;
  logic bb = 0;
  logic [1:0] c;
  
  function automatic logic foo(logic x, logic y);
    return x && y;
  endfunction
  
  always_comb begin
    c = 0;
    unique0 if (a) begin
      c = 1;
    end else if (foo(b, bb)) begin
      c = 2;
    end else begin
      c = 3;
    end
  end
  
  initial begin
    #1;
    a <= 1;
    b <= 0;
    bb <= 0;
    #1;
    a <= 0;
    b <= 1;
    bb <= 1;
    #1;
  end
  
  initial begin
    $monitor("%t : %b %b %b %0d", $time(), a, b, bb, c);
  end
  
endmodule

Output:

                   0 : 0 0 0 0
                   1 : 1 0 0 1
                   2 : 0 1 1 0

The frequency of my posts is only slightly higher than the frequency of snowfalls in Barcelona. A half-joking experiment on what happens if you put an AI into the technical interview.

A short and light reading about one particular bad UVM agent design practice and how to avoid it. May be interesting for not very experienced engineers and those only making their first steps in UVM.

https://publish.obsidian.md/zvord/Blog/Splitting+the+responsibility+pie

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A broadcast channel to announce new posts in my blog: https://publish.obsidian.md/zvord/Welcome+to+Verification+Haven

Channel created