🟨 FPGA Design Engineer | 3 year(s) | Middle | IC
▫️ ASML | Semiconductor manufacturing
▫️ Netherlands | Veldhoven
Office 🏢
Required languages: 🇬🇧
Skills: systemverilog, linux, git, python, c
Tags: #yellow #research_and_development #embedded
👉 Contacts and Full Description
Post #361174
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