Collection of IP-cores for FPGA & ASIC written on Verilog/VHDL
#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera
PS: also might be intresting @fpgasic
Post #3
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GRVI is an FPGA-efficient RISC-V RV32I soft processor core, hand technology mapped and floorplanned for best performance/area as a processing element (PE) in a parallel processor. GRVI implements a 2 or 3 stage single issue pipeline, typically consumes 320 6-LUTS in a Xilinx UltraScale FPGA, and currently runs at 300-375 MHz in a Kintex UltraScale (-2) in a standalone configuration with most favorable placement of local BRAMs.
http://fpga.org/grvi-phalanx/
#RISC-V #ParallelProcessing #NOC #ParallelComputing #Phalanx #Hoplite
http://fpga.org/grvi-phalanx/
#RISC-V #ParallelProcessing #NOC #ParallelComputing #Phalanx #Hoplite
