For decades, the semiconductor industry has boosted computing power by making transistors smaller and fitting more of them onto a single chip. That strategy has fueled remarkable advances in electronics, but it is now approaching fundamental physical limits. As devices shrink toward atomic scales, engineers must contend with the constraints of material properties and the effects of quantum mechanics.

Researchers believe the next major advance may come not from making chips smaller, but from building them upward.

A team at the University of Illinois Grainger College of Engineering has demonstrated a new way to stack layers of silicon circuits directly on top of one another, creating compact three-dimensional chips that could deliver greater computing power while using less energy. Their work, published in Nature, overcomes a major obstacle that has long prevented widespread adoption of this approach.

“Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient,” said Qing Cao, a professor of materials science and engineering at Illinois Grainger Engineering.