/* Категория HDL для FPGA/ASIC */▫️ https://github.com/openhwgroup
▫️ https://github.com/bespoke-silicon-group
▫️ https://github.com/pulp-platform
▫️ https://github.com/ultraembedded
▫️ https://github.com/enjoy-digital
▫️ https://github.com/litex-hub
▫️ https://github.com/RoaLogic
▫️ https://github.com/lowRISC
▫️ https://github.com/FPGA-Research-Manchester
▫️ https://github.com/IObundle
* - по версии @embedoka